Hello,
I am trying to write a code for bidirectional buffer.
In the making of bidirectional buffer, although the logic seems simple, I face problem.
Pad not given any value in testbench
• When enable is ‘1’ Pad(I/O) is driven by Din(input port). Dout(output port) is been driven by Pad.
Pad Given a value in TestBench
• When enable is ‘0’ Dout is driven by Pad, but Pad stops to be driven by Din, in earlier stages. i.e when enable was ‘1’ Pad should have been equal to Din, but its “U” the undefined state.
My code I am currently using.
architecture Behavioral of bidir is
signal wrt_on_pad : STD_LOGIC_VECTOR(7 downto 0);
signal rd_frm_pad : STD_LOGIC_VECTOR(7 downto 0);
begin
wrt_on_pad <= din;
rd_frm_pad <= pad when e = '0' else (others => 'Z');
pad <= wrt_on_pad when e = '1';
dout <= rd_frm_pad;
end Behavioral;
In test bench :
din <= "11111111"
wait for 10ns;
e <= '1';
wait for 10ns;
pad <= "00000000";
e<= '0';
I am trying to write a code for bidirectional buffer.
In the making of bidirectional buffer, although the logic seems simple, I face problem.
Pad not given any value in testbench
• When enable is ‘1’ Pad(I/O) is driven by Din(input port). Dout(output port) is been driven by Pad.
Pad Given a value in TestBench
• When enable is ‘0’ Dout is driven by Pad, but Pad stops to be driven by Din, in earlier stages. i.e when enable was ‘1’ Pad should have been equal to Din, but its “U” the undefined state.
My code I am currently using.
architecture Behavioral of bidir is
signal wrt_on_pad : STD_LOGIC_VECTOR(7 downto 0);
signal rd_frm_pad : STD_LOGIC_VECTOR(7 downto 0);
begin
wrt_on_pad <= din;
rd_frm_pad <= pad when e = '0' else (others => 'Z');
pad <= wrt_on_pad when e = '1';
dout <= rd_frm_pad;
end Behavioral;
In test bench :
din <= "11111111"
wait for 10ns;
e <= '1';
wait for 10ns;
pad <= "00000000";
e<= '0';