Basic Clock division help

[vb001]

Hi there,
I just need to divide a 50mhz clock, into a 1hz one.
being new to vhdl, im not sure about the size of the logic_vector?

Im also unsure about the two comparing statements CT1<50.etc
and how to create an accurate 1 hz, with an accurate 50% duty cycle..
thanks for your time, i'd be grateful for any help at all.
heres the code.

Vish

entity Cntr50 is
Port (CLOCK : in STD_LOGIC;
C_OUT1 : out STD_LOGIC);
end Cntr50;

architecture Cntr50_Arch of Cntr50 is
signal CT1: STD_LOGIC_VECTOR (24 downto 0);
begin
process (CLOCK)

begin
if (rising_edge(CLOCK)) then
if CT1 < 50E6 then
CT1 <= CT1 + 1;
else
CT1 <= "0000000000000000000000000";
end if;

if CT1 < 25E6 then
C_OUT1 <= '0';
else
C_OUT1 <='1';
end if;

end if;
end process;
end Cntr50_Arch;

 

[PaulieQ]

Servus,

Below you can find a method in which you can generate a 1HZ from 50MHz. I don't know if it is the best but it works.

The value of the constant FACTOR is used for dividing the main clock.

Herz = Main clock frequency/FACTOR.

(Hint: Don't try to simulate it with FACTOR = 50.000.000. In this case the simulation time must be 1sec and probably Windows will generate a NOT RESPONDING for simulator. Verify it with a smaller Factor, e.g. 50.000 -> 1kHz.)

----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------

entity simplu is
end simplu;

architecture simaisimplu of simplu is
signal a,b,herz: std_logic := '0';
signal clk: std_logic := '1';
constant factor : natural := 50000000;
begin
clk <= not clk after 10 ns; -- 50MHz gen.

div: process (clk)
variable counter : natural :=0;
begin
if rising_edge(clk) then
if counter = factor/2-1 then
herz <= not herz;
counter := 0;
else
counter:= counter + 1;
end if;
end if;
end process;
end simaisimplu;



Best regards,
Paulie