attribute DELAYED is unsupported in Xilinx ISE

[serom]

Hi,

I am using ISE fundation 7.01

I just want to synthesize a VHDL code that contains the expression "Clk'DELAYED(1 ns)"
But each time I want to use the "DELAYED" attribute, I have the following error:
The predefined attribute DELAYED is unsupported.

What can I do to permit to ISE to recognise the DELAYED attribut

Thank in advance

Cheers

Romain

 

[jeandelfrigo]

Serom,

Delayed is typically an attribute You would use to simulate a LUT delay or Tco delay or something like this.

You would use it to make a simulation more like reality.

When you use Xilinx ISE and you want to synthesize and implement your design you cannot use these kinds of attributes, because implemented hardware does not have any time notion other than clock periods or better yet clock cycles.

What you can do is use hardware delay chains like in a Xilinx Virtex2Pro or Virtex 4 device, or LUT routing delays.
An example where you would use this is in a DDR controller where you want to shift the DQS signal from the RAM half a clock to the data in order to clock the data on this DQS.

You have to keep in mind that hardware has no time knowledge.So for code you want to synthesize you need to use the resources available in the target device.
It requires some knowledge of the target device by reading the datasheet and also taking a look at synthesis and implementation constraints for Xilinx devices.

I'm sorry to say but VHDL and hardware design is less flexible than software like C or JAVA. It demands more detailed thought of the designer.
You need to keep in mind at a certain abtstraction of course how you would build it with the given resources in the device.

For simulation purposes you can do a lot more in VHDL.

I hope this has helped you a litle.

regards

jeandelfrigo