Atributes in VHDL

[superosjecaj]

Hi,

i would like to design different adders such as ripple, carry select etc., but i dont know how can I tell the VHDL compiler not to collapse carry nodes ie make from every adder Carry lookahead adder.
I used to program in ABEL; there that could be done this way:
c1..c8 node istype 'com,keep'; (definition of carry nodes)
what i need is VHDL equivalent to 'keep'.

Thanks in advance,
Superosjecaj