assigning values to generics

[shredzone]

I am new to VHDL. When instantiating a component I need
to assign a value to the generic which depends on another
generic parameter declared in the entity.
Is some form of conditional assignment possible for generics?

I hope the above makes sense.

 

[jeandelfrigo]

shredzone,

Interesting question. I've never done something like this before, that is that I can remember at this time.

However I think it is possible to pass a generic value to a lower hierarchy component by making an expression based on other generics.
I guess the only limitation is that you should limit the operators to those that or supported by the generic type (e.g. natural, integer, std_logic, ...).
Also you should make sure you have the required packages (ieee libs) included.

I guess this should work, but the only way to do this is to try it.

Something I do know is that simulators, like modelsim tend to have problems when you use expressions in the port or generic map, so if you want to simulate the code you will need to take a detour via a extra generic or signal.
But this is an issue of the simulator and not of the language.

regards,

jeandelfrigo