array and generate probleme for FPGA

[vince00001]

Hello,

I use Quartus II version 7.0 Webedition for FPGA. In order to implement video application I need to generate 70 lpm_dff register and link the first register output with the second register input and the second output with the third input etc....
The first register is linked with right signal (STD_LOGIC_VECTOR (7 downto 0)) and every wire beetwen the different register are std_logic_vector (7 downto 0) in an array (zR_array).
But error report say zR_array does not agree with the usage as std_logic_vector


------------------------BLOCK SIGNALS-----------------------

ENTITY WinBLK IS
PORT
(
Right : IN STD_LOGIC_VECTOR (7 downto 0);
Left : IN STD_LOGIC_VECTOR (7 downto 0);
clk : IN STD_LOGIC;
);
END WinBLK;

ARCHITECTURE WinProcess OF WinBLK IS

--------------------CONSTANT-------------------------------
constant Maxfor : integer := 69;

--------------INTERNAL SIGNALS AND ARRAY-------------------

TYPE zR_array IS ARRAY (natural range <>) OF std_logic_vector (7 downto 0);

-----------------COMPONENT BLOCKS-------------------------

-----------REGISTER 8 Bits for Right sample (70)
component lpm_dff8

PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enable : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END component lpm_dff8;

BEGIN

-----------------------MAIN PROCESS------------------------

g1:for i in 0 to (Maxfor +1) GENERATE

g2:if i = 0 generate
dffx: lpm_dff8 port map ( clk, Right, EnableRight, zR_array );--regRN
end generate g2;

g3:if (i > 0) and i < (Maxfor) generate
-- dffx: lpm_dff8 port map ( clk, zR_array(i), EnableRight, zR_array(i+1) );--regRN
end generate g3;

g4:if i <= (Maxfor + 1) generate
-- dffx: lpm_dff8 port map ( clk, zR_array(i), EnableRight, Right_INT );--regRN
end generate g4;

END GENERATE g1;

h1:for i in 0 to (Maxfor+1) GENERATE

h2:if (i > 0) and i < (Maxfor+1) generate
-- dffy: lpm_dff8 port map ( clk, Left_INT, EnableRight, zL_array(i+1) );--regRN
end generate h2;

END GENERATE h1;

END WinProcess;

ERROR REPORT:

Error (10476): VHDL error at winBLK.vhd(97): type of identifier "zR_array" does not agree with its usage as std_logic_vector type
Error (10558): VHDL error at winBLK.vhd(97): cannot associate formal port "q" of mode "out" with an expression

Can someone help???

Thanks in advance for your answer.
Regards,
Vince

 

[leandroventurini]

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look the forum

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bye

 

[BertVhdl]

Hi Vince,

I think the problem is that output Q at component lpm_dff8 is an std_logic_vector and zR_array is an array of vectors.


If you want to pass one vector in zR_array to Q, then you need to index it:

g2:if i = 0 generate
     dffx: lpm_dff8 port map ( clk, Right, EnableRight, zR_array[b](0)[/b] );   
end generate g2;

If you want to pass the complete array to Q, then you need to make Q an array too.

Hope this helps!

Bert