Altera VHDL question

[niner710]

Hi,

I am a newbie to VHDL. I had a question on this piece of code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--library UNISIM;
--use UNISIM.VComponents.all;

entity CA_MUX_CNTRL is
Port ( SIN : in std_logic_vector(5 downto 0);
MUX_SEL : out std_logic_vector(7 downto 0)
);
end CA_MUX_CNTRL;

architecture CA_MUX_CNTRL_arch of CA_MUX_CNTRL is

begin

with SIN select
MUX_SEL<= "00000000" when "000000",
"10110001" when "000001", "11000010" when "000010", CA_MUX_CNTRL_arch;

I am using altera for a circuit layout and I need to grab the outputs of the multiplexer and feed them to another part of the circuit, but the symbol that i compile from this piece of code only gives me the output as one std_logic_vector line. How do i change the code so that instead of MUX_SEL being a std_logic_vector of 8 bits I can get Mux_sel(0),Mux_sel(1)....Mux_sel(7), and feed each output line to another part of my circuit. THxs!

 

[mptech]

better to separate all bits of logic_vector like below and give to std_logic output:

tmp1<= MUX_SEL(0);
tmp2<=MUX_SEL(1);
and so on;

thus you will get all bits of logic_vector as separated std_logic.

 

[jeandelfrigo]

Niner710,

Is this entity the toplevel of your design?

because if this is the only code in your FPGA or CPLD then you can easily route the different one bit slices of this vector to different pins that exit your device by assigning them to the correct pins.

If it is not the toplevel of your design but you want to route the different bits to other components in your design the just connect them in the port map like this

i_A : componentA
port map(
x => whatever,
y => whatever,
z => mux_sel(0)
);

i_B : componentB
port map(
x => whatever,
y => whatever,
z => mux_sel(5)
);

i_c : componentC
port map(
x => whatever,
y => whatever,
z => mux_sel(4 downto 1)
);

in the first two components Z is a std_logic;
in the last component Z is a std_logic_vector(3 downto 0)

I hope this is usefull for you?
I you have any questions just ask.

regards jeandelfrigo