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Algorithm Describing and VHDL

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Dimitrova

Technical User
Dec 10, 2003
1
PL
Is it possible to describe just an algorithm in VHDL and how?
 

Yes it is.

If your target is simulation only you just write it like in any computer language. E.g. you can write a procedure or function.

If your target is hardware you must additionally obey several rules.
For algorithms implementation the solution could be e.g. the finite state machine, which is something like a program but implemented in hardware directly.

rgds

 
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