Adding Source

[sheenjrg]

How can I add a new vhdl file to an existing project(Xilinx project navigator) such that it is nested inside one of the module?

 

[RVSachin]

Should be very simple.

Go to Projects on Menu bar ---> Add Source.
A pop-up window will ask you choose the file from a particular directory. After selecting file to add, another window will ask you to 'choose source type' like whether the selected file is a source file, a package, or a testbench. Choose appropriately and then, the file is added to the project. ISE will automatically insert the file within the module as long as the top module is selected correctly.

 

[sheenjrg]

how do I select the top module?
like for exampleif I already have a project

counter_top
|
|--tb_counter
|--counter_1
|--counter_2


how do I insert a vhd file counter_3 between counter_1 and counter_2 such that it comes like this

counter_top
|
|--tb_counter
|--counter_1
| |--counter_3
|
|--counter_2

if I add a source from the menu using add source-- VHDL module it adds as

---counter_top
| |
| |--tb_counter
| |--counter_1
| |--counter_2
|
|---counter_3

 

[sheenjrg]

All right guys got it don't wory abt it