Adding and Subtracting Vectors

[mikeymik]

I'm just new to vhdl, I'm having problems adding specific vectors, i keep getting a type mismatch error. I'm just looking to do something simple like:

vec:STD_LOGIC_VECTOR(7 downto 0);

I<= (vec(2)+(2*vec(3))+vec(4))-((vec(5)+(2*vec(6))+vec(7));

However I seem to declare them, i get the same message.
Please someone help.

 

[melzayed]

+ and - are arithmetic operators and can only be used with arithmetic types such as integer.

When you declare a std_logic type. You must use logical operators such as OR, AND, NAND, etc..

Hope this helps

M.

 

[RVSachin]

Arithmetic operators can be used on std_logic_vector data types provided you use the necessary package.

As far as performing the arith opertions on single bit is concerned, you can declare a single bit as std_logic_vector(0 downto 0 ) instead of doing it as std_logic.

Note that, whenever * operator is used, the size of the result has to be sum of the widths of operands.

If in your code, if you eliminate the * operator, you can make it work by modifying it as follows:
[Note the usage of 'unsigned' package and the way the output I has been declared.

--________________________________

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bitadd is
port(
vec: in STD_LOGIC_VECTOR(7 downto 0);
i: out std_logic_vector(0 downto 0));--std_logic);
end entity bitadd;

architecture rtl of bitadd is
begin
i <= (vec(2 downto 2)+(vec(3 downto 3))+vec(4 downto 4)) - ((vec(5 downto 5)+(vec(6 downto 6))+vec(7 downto 7)));
end rtl;
--_________________________