A question about VHDL and simulation with modelsim

[betal]

Hi everybody, I'm working with Xilinx ISE and modelsim. My code has three processes. Two are synchronized with a global clock and the other is not.
That's what I do there(this is not code):

process 1 (synchronized through clk='1' and clk'event)

next_cnt<=cnt (cnt is a variable)

process 2 (synchronized through clk='1' and clk'event)

actual_cnt<=next_cnt (both are signals)

process 3 (not synchronized )

rdy_cnt<=actual_cnt


The problem is that when I see the value of rdy_cnt on modelsim it is half cycle delayed compared with
actual_cnt.

Hope someone can help me to understand it!!

 

[jeandelfrigo]

Betal,

Are you sure that Actual_cnt is in the sensitivity list of process3 ?

The other thing that might be the case is delta cycle delay,
but if it is or not is hard to determine from the information you provided.

regards

jeandelfrigo