If anyone has a FNF clock cabling diagram please send it to me at cgiannino@nacr.com Please.
I have a system that is giving me some FiGi errors 007, 005, 018 with PLL_LOL_78M
I need to review the cabling as I forgot how all of this fits together. Also I have a tech that wants to swap clocks because of this saying these are being generated by the in active cores clock. I dont think so.....but need the diagram anyway
thanks
Mel
I have a system that is giving me some FiGi errors 007, 005, 018 with PLL_LOL_78M
I need to review the cabling as I forgot how all of this fits together. Also I have a tech that wants to swap clocks because of this saying these are being generated by the in active cores clock. I dont think so.....but need the diagram anyway
thanks
Mel