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4K addressablitly with single base register

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programmercts

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Feb 20, 2003
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HI
Is it mandatory that with one base register we can only access upto 4k addressablity of particular code. Although with one register we can go beyond 4K addressablity. But normally in assembly it is always that with one base register we only access upto 4K. And if code size is greater than 4K we will use two base register upto 8K.
So is it the limitation of OS my means to say that PAGE SIZE issued by OS are also of 4K. so if code is greater than 4K, two pages will be used & and we have to use different base register for different page.
Or it is due the displacements used in opcodes they are limited to three nibbels (FFF). That makes it to maximum use of 4K in a single code with one base register.
So somebody know what is the actual reason of using 4K with single base register.
 
hmm,

in PE+PG mode logical memory is linear and can be upto 4Gb and your code or data segment can be 4Gb is size.

logical memory is the linear memory defined for a task.
physical memory is actually what the PC has.

the tasks logical memory is mapped to the physical memory and this is done using PD/PT tables.

each PD/PT is 4k in size giving 1024 4 byte entries.

each task has 1 PD (page directory) pointed in physical memory by CR3(PDBR).

each entry in the PD points to a PT (page table), each entry in the PT points to a 4k physical memory area.

a PT maps 4Mb of linear memory (1024 4k pages=4Mb) each 4k page can be located anyway in physical memory ie you could map each 4k page to the same bass address( this would give a task 4Mb of linear memory but address 0h would be the same byte as 01000h and 02000h and 03000h and so on.

PD works in the same way. the PTs can be located anywhere in physical memmory and each PD entry can point to any PT. so if you made all the PD entries the same every 4Mb would be the same.

obviously this isnt practical but im just trying to explain how it works.

PT= 1024 entries of 4k = 4Mb
PD= 1024 entries of PTs (4Mb)= 4Gb

each task can of corse can share the same physical memory.

so once you have assigned task linear memory to physical memory you make your GDT or LDT entry (code or data selector) the size of your linear memory (maximum of 4Gb). if you make your code size bigger than your map you will create an exception because the processor doesnt know what memory to use.

if the OS only gives memory in 4k pages then you need to ask for more.

did i help? or can you rephrase the question.
straiph

"There are 10 types of people in this world, those who know binary and those who don't!"
 
What type computer are you talking about?

The term "base register" makes me think its an IBM mainframe. If so, the limit is due to the size of the three-nibble "displacement" like you speculated.

You are right that the page size is 4K, but that does not effect the usage of base registers. You can see this with instructions that can use an index register. Those instructions can use a base register, plus the index register to access well beyond 4K. Also, the base register does not have to point to the start of a page, you can address a 4k "chunk" of storage that starts on one page and ends on another.

In general, one base register can be used to address 4k at any point in time. You can break a program into several routines and load the base register at the top of each. This would allow you to use a single base register no matter how long your program is. But each routine would have to contain its own variables/constants/etc.

On newer mainframes you can also write "baseless code" that does not depend on base registers. You have to use jumps and relative branches instead of the older branch instructions that depend on a base register. Of course there's more to "baseless coding" just branching. Look at the latest assembler doc from IBM for a complete explanation.

If you are talking about a PC, the term "base register" doesn't quite fit. For a PC I suggest you read the response from Straiph, and rephrase the question if you need more info.

Hope this helps.
 
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