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4-bit comparator and master slave flip flop
- Thread starter crazyduck
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stevieblunder
Technical User
The idea of a "high-level" language like VHDL is that you don't worry much about flip-flops. You let the compiler worry about that. If you define two integer signals range (0-15) and compare them "out <= A < B;", "out" will probably compile to a 4 bit comparator.
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