3x3 Determinant Calculation state problem

[conanind]

I have designed a 3x3 determinant calculation chip. I have 5 states. However, simulation stops due to fatal error in the 4th state. My code is below:

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity determinant3x3 is
port(clk,reset:in std_logic;
a11,a12,a13,a21,a22,a23,a31,a32,a33:in std_logic_vector(7 downto 0);
determinantut std_logic_vector(24 downto 0);
doneut std_logic);
end determinant3x3;

architecture Structure of determinant3x3 is
--Intermediate signal declarations
signal detM11_res:std_logic_vector(15 downto 0);
signal detM12_res:std_logic_vector(15 downto 0);
signal detM13_res:std_logic_vector(15 downto 0);
signal SubResult_res:std_logic_vector(24 downto 0);
signal temp:std_logic_vector(24 downto 0);


--State declaration
type state_type is (Reset_state,detM11,detM12,detM13,SubResult,Result);
signal state: state_type;

begin
--Control Path
control_pathrocess(clk,reset)--clocked process
begin
if reset = '1' then
state <= Reset_state;
elsif clk'event and clk = '1' then
case state is
when Reset_state =>
state <= detM11;
when detM11=>
state <= detM12;
when detM12=>
state <= detM13;
when detM13=>
state <= SubResult;
when SubResult=>
state <= Result;
when Result=>
state <= detM11;
end case;
end if;
end process control_path;


--Data Path
data_pathrocess(state)--combinatorial process

--these are declared as variables, because these have to be assigned after the multiplications are performed
--so it has to be a blocking assignment for them. If these were defined as signals, it would be a non-blocking
--assignment and we would get the detM11_sub1's and detM11sub2's previous results, which we don't want.
variable detM11_sub1:std_logic_vector(15 downto 0);
variable detM11_sub2:std_logic_vector(15 downto 0);
variable detM12_sub1:std_logic_vector(15 downto 0);
variable detM12_sub2:std_logic_vector(15 downto 0);
variable detM13_sub1:std_logic_vector(15 downto 0);
variable detM13_sub2:std_logic_vector(15 downto 0);
variable SubResult_sub1:std_logic_vector(24 downto 0);
variable SubResult_sub2:std_logic_vector(24 downto 0);
variable Result_sub1:std_logic_vector(24 downto 0);

begin
case state is
when Reset_state=>
done <= '0';
when detM11=>
detM11_sub1 := a22*a33;
detM11_sub2 := a23*a32;
detM11_res <= detM11_sub1-detM11_sub2;
when detM12=>
detM12_sub1 := a21*a33;
detM12_sub2 := a23*a31;
detM12_res <= detM12_sub1-detM12_sub2;
when detM13=>
detM13_sub1 := a21*a32;
detM13_sub2 := a22*a31;
detM13_res <= detM13_sub1- detM13_sub2;
when SubResult=>
SubResult_sub1 := a11*detM11_res;
-- SubResult_sub2 := a12*detM12_res;
SubResult_res <= SubResult_sub1 - SubResult_sub2;
when Result=>
-- Result_sub1 := a13*detM13_res;
temp <= Result_sub1 + SubResult_res;
done <= '1';
end case;
determinant <= temp;
end process data_path;


end Structure;
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Here, on the state "SubResult", the first line causes the error. But I don't understand why? Can't we assign signals to variables?

Thank you