3-bit synchronous counter 1

[amisophie]

This is my code. I get the error: ERROR:HDLParsers:164 - "C:/Xilinx/3-bitcounter/3bc.vhd" Line 31. parse error, unexpected INTEGER_LITERAL, expecting IDENTIFIER. Does anyone know what I can do to correct this. I also get the warning: WARNING:HDLParsers:3481 - Library work has no units. Did not save reference file "xst/work/hdllib.ref" for it.

entity 3bc is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
sel : in STD_LOGIC;
q : out STD_LOGIC);
end 3bc;

architecture Behavioral of 3bc is
begin
process(clk,reset)
begin
if reset = '1' then
q <= "000";
else if rising_edge(clk) and reset ='0' and sel = '0' then
q <= q+1;
if rising_edge(clk) and reset = '0' and sel = '1' then
q <= q+2;
end if;
end if;
end process;

end Behavioral;

 

[jeandelfrigo]

Amisophie,

To begin with, it is not a good idea to start names in VHDL with a figure. This goes for Signal names, constant names, processnames, entity names, ... in short any kind of names.

So I propose you rename your entity to BinCounter_3Bit or BinCount3bit or whatever name you like that does not start with a figure.
I know and I often make the same "mistake" that comming up with names is sometimes a difficult process, but when you choose a name, especially for a component or entity it is advisable to select a name that clearly indicates what the peace of code does.

In 3bc that is not really clear. Is it a three bit binary counter or gray counter or what.
Yeah I know when you look at the code it's easy to see what the thing is, but imagine you have to browse a 2500 lines vhdl file to figure out what the code does.

Another way to avoid silly super long and complex names is to add some comment in the top of your files describing what it does and how to interface the component.

So this error : C:/Xilinx/3-bitcounter/3bc.vhd" Line 31. parse error, unexpected INTEGER_LITERAL is about the 3 in 3bc.

Second remark: Normally you also have to add your library declarations in the top of the VHDL file. (IEEE libs).
Now I imagine you left them out of your code extract, but if you didn't make sure you add them.

I guess the warning (WARNING:HDLParsers:3481 - Library work has no units. Did not save reference file "xst/work/hdllib.ref") is a result of the error.

Because there is an error in your entity declaration the tool cannot create anything in the work library. Xilinx and also other vendor tools have the habbit of creating a massive amount of errors and warnings and other crap just because there's a comma out of place. Sometimes fixing one single syntax error can reduce the error messages by 2.

Some other remarks :

I do not know if this is the only peace of code you use in the design, but you have some redundancy in it. Probably the tool will see this and optimize it but it's nicer to write your code clean from start. What I mean is this. You have a syncronous process with an asynchronous reset. So If the reset is 1 you reset the counter, else if a rising edge on the clock you want to either increment the counter by one or two depending on the value of sel. The reset = '0' is not needed because it is enclosed in the else condition. Also you can write elsif instead of else if.

Also you need to make q a std_logic_vector(2 downto 0).
The tool hasn't given an error yet but it will as soon as the first eror is solved

This is a proposal :

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity BinCount3bit is
port(
clk : in std_logic;
reset : in std_logic;
sel : in std_logic;
q : out std_logic_vector(2 downto 0)
end BinCount3bit;

architecture behavioral of BinCount3bit is
begin

process(clk,reset)
begin
if reset = '1' then
q <= (others => '0');
elsif(rising_edge(clk))then
if sel = '0' then
q <= q+1;
else
q <= q+2;
end if;
end if;
end process;

end behavioral;

The (others => '0') is an easy way of making the vector reset to zero without taking into account the size of the vector. So if you want to change it to 6 bit you just have to change the size of the port.

I think this will help you further and I hope all is clear, if not just ask me for more explanation .

Best of luck

regards

jeandelfrigo