2 entities in onefile

[vivien88]

Hi all,

I'm completely new in VHDL and I need help.
I have a very simple example in VHDL and want to compile it with vhdlan.

When I have to separate files they compile correctly with 0 EXIT_STATUS.
One file contains:

library IEEE;
use IEEE.std_logic_1164.all;

entity first is
port (
simple : in std_logic
);
end first;

architecture first_rtl of first is
begin
end first_rtl;

Second file contains:

entity second is
port (
simple : in std_logic
);
end second;

architecture second_rtl of second is
begin
end second_rtl;

But when I put them together in one file, compilation fails giving this error message:
"The symbol 'STD_LOGIC' does not have a visible declaration."

I want to have these entities in one file, what can I do to eliminate errors and make compilation to pass.

Thank you!

P.S. I forgot to say that I'm using this command:
vhdlan -w WORK file.vhd