2-digit BCD counter help!!

[impedance]

Hey there people,

I am just working on this lab.. in writing a VHDL code for a 2-digit BCD counter with active-LOW asynchronous clear, active-High synchronous load, and an Active-High count enable.

I am just wondering, if u guyz could help me out.??

thanks
dino.

 

[impedance]

sorry forgot to mention:

The counter must count up from 00 to 09, then 10 to 19, and so on until it reaches 99. At that point the counter must roll over to 00. THe parallel inputs should load any value from 0 to 9 on each digit. If a parallel binary input falls outside the valid BCD range (1010 to 1111) for either digit, the circuit should set that digit to 9 when the parallel input is loaded.

 

[jeandelfrigo]

Hello Impedance,

Here you go :

--*****************************************************************************
-- Description of a two digit BCD counter
--
-- ports :
--
-- Clk : Clock signal
-- Clear : Asynchronous active low clear signal
-- Load : Synchronous active high load signal
-- Enable : Synchronous active high count enable signal
-- DataIn : 8 bit input port for preset of counter
-- 7 downto 4 for most significant digit
-- 3 downto 0 for least significant digit
-- DataOut : 8 bit output port for BCD counter
-- 7 downto 4 for most significant digit
-- 3 downto 0 for least significant digit
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity bcd is
port(
Clk : in std_logic;
Clear : in std_logic;
Load : in std_logic;
Enable : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
DataOut : out std_logic_vector(7 downto 0)
end bcd;

architecture RTL of bcd
-- signal declaration
signal CountL : std_logic_vector(3 downto 0);
signal CountL : std_logic_vector(3 downto 0);
signal next_CountH : std_logic_vector(3 downto 0);
signal next_CountH : std_logic_vector(3 downto 0);
signal CountL_TC : std_logic;

begin

procCountL: process(Clk,Clear)
begin
if (Clear = '0')then
CountL <= (others => '0');
elsif(Clk'event and Clk = '1')then
if (Load = '1')then
if (DataIn(3 downto 0) > "1001")then
CountL <= "1001";
else
CountL <= DataIn(3 downto 0);
end if;
elsif(Enable = '1')then
if (CountL = "1001")then
CountL <= (others => '0');
else
CountL <= CountL + 1;
end if;
end if;
end if;
end process procCountL;

CountL_TC <= '1' when CountL = "1001" else '0';

procCountH: process(Clk,Clear)
begin
if (Clear = '0')then
CountH <= (others => '0');
elsif(Clk'event and Clk = '1')then
if (Load = '1')then
if (DataIn(7 downto 4) > "1001")then
CountH <= "1001";
else
CountH <= DataIn(7 downto 4);
end if;
elsif(Enable = '1' and CountL_TC = '1')then
if (CountH = "1001")then
CountH <= (others => '0');
else
CountH <= CountH + 1;
end if;
end if;
end if;
end process procCountH;

DataOut <= CountH & CountL;

end RTL;

I did not know if the output had to be split up but you can do that yourself I think.

regards,

Jeandelfrigo

 

[jeandelfrigo]

Hello Impedance,

Sorry but there were a few syntax errors in the previous code and also some unused signals. I did simulate the code untill just now.

Here is the correct code, all situations have been simulated.

--*****************************************************************************
-- Description of a two digit BCD counter
--
-- ports :
--
-- Clk : Clock signal
-- Clear : Asynchronous active low clear signal
-- Load : Synchronous active high load signal
-- Enable : Synchronous active high count enable signal
-- DataIn : 8 bit input port for preset of counter
-- 7 downto 4 for most significant digit
-- 3 downto 0 for least significant digit
-- DataOut : 8 bit output port for BCD counter
-- 7 downto 4 for most significant digit
-- 3 downto 0 for least significant digit
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity bcd is
port(
Clk : in std_logic;
Clear : in std_logic;
Load : in std_logic;
Enable : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
DataOut : out std_logic_vector(7 downto 0)
);
end bcd;

architecture RTL of bcd is
-- signal declaration
signal CountL : std_logic_vector(3 downto 0);
signal CountH : std_logic_vector(3 downto 0);
signal CountL_TC : std_logic;

begin

procCountL: process(Clk,Clear)
begin
if (Clear = '0')then
CountL <= (others => '0');
elsif(Clk'event and Clk = '1')then
if (Load = '1')then
if (DataIn(3 downto 0) > "1001")then
CountL <= "1001";
else
CountL <= DataIn(3 downto 0);
end if;
elsif(Enable = '1')then
if (CountL = "1001")then
CountL <= (others => '0');
else
CountL <= CountL + 1;
end if;
end if;
end if;
end process procCountL;

CountL_TC <= '1' when CountL = "1001" else '0';

procCountH: process(Clk,Clear)
begin
if (Clear = '0')then
CountH <= (others => '0');
elsif(Clk'event and Clk = '1')then
if (Load = '1')then
if (DataIn(7 downto 4) > "1001")then
CountH <= "1001";
else
CountH <= DataIn(7 downto 4);
end if;
elsif(Enable = '1' and CountL_TC = '1')then
if (CountH = "1001")then
CountH <= (others => '0');
else
CountH <= CountH + 1;
end if;
end if;
end if;
end process procCountH;

DataOut <= CountH & CountL;

end RTL;

As you can see this is really simple code.

If you simulate this code, set the radix for
DataIn, DataOut , CountH and CountL in hex then it is very easy to see both digits in the single vector.

regards
Jeandelfrigo