I need help with the design of a BCD counter.
The requirements:
- 1 digit BCD counter
- a synchronous (4?bit) up/down decade counter with output Q that works as follows:
-All state changes occur on the rising edge of the CLK input, except the asynchronous clear (CLR). When CLR = 0, the counter is reset regardless of the
values of the other inputs.
- If the LOAD = ENABLE = 1, the data input D is loaded into the counter.
- If LOAD = 0 and ENABLE = UP = 1, the counter is incremented.
- If LOAD = 0, ENABLE = 1, and UP = 0, the counter is decremented.
- If ENABLE = UP = 1, the carry output (CO) = 1 when the counter is in state 9.
- If ENABLE = 1 and UP = 0, the carry output (CO) = 1 when the counter is in state 0.
- CLK period of 10 ns.
The requirements:
- 1 digit BCD counter
- a synchronous (4?bit) up/down decade counter with output Q that works as follows:
-All state changes occur on the rising edge of the CLK input, except the asynchronous clear (CLR). When CLR = 0, the counter is reset regardless of the
values of the other inputs.
- If the LOAD = ENABLE = 1, the data input D is loaded into the counter.
- If LOAD = 0 and ENABLE = UP = 1, the counter is incremented.
- If LOAD = 0, ENABLE = 1, and UP = 0, the counter is decremented.
- If ENABLE = UP = 1, the carry output (CO) = 1 when the counter is in state 9.
- If ENABLE = 1 and UP = 0, the carry output (CO) = 1 when the counter is in state 0.
- CLK period of 10 ns.