I'm sorry forgot to mention where might line 22 be....
begin
process(D, CK)
variable LastEventOnD, LastEventonCK: TIME;
begin
if (D'event) then <--- Line 22
assert (NOW = 0 ns) or (NOW - LastEventOnCK) >= HOLD_TIME
report "Hold time to short"...
I'm using Quartus to compile a DFLIPFLOP that i had created originally for Modelsim Altera, on the Modelsim it compiles great with no error on Quartus II i get the following error:
Error: VHDL Case Statement or If Statement error at DFLIPFLOP.vhd(22): can't synthesize condition that contains an...
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