Adithya,
you are hardcoding rst<= '0'; at the top of your code, hence the condition if(rst='1') is never true. Synthesis will find that everything until the corresponding end if; is never reached and gets optimised out. Also, do not need to have more than (starting, clk) in your sensitivity list
You are assigning ADC to Data, so assuming that they are of the same type you should write.
when Read => Data <= ADC;
Ticks are used for properties such as
when Read => Data <= ADC(Data'range);
if Data and ADC are of different width for instance.
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