I am new to VHDL and am trying to program an 8-bit carry look-ahead adder. My probelm is not the code, but trying to test it in Modelsim. I can see when I run the waveforms that the addition works atleast, but I want to know if my carry_in and carry_out bits are correct at each stage.
Here is my...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.