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There might be other problems.
Hi, VHDLguy:
Thanks for your reply. For my systhesis tool, LeonardoSpectrum for Atmel, Version: 2002c.37_OEM_Atmel, there is no progma related with the signal name usage. At least in the help I could not find one through search.
By the way, I found my VHDL code is not well designed from...
Hi,
I am working with an FPGA design of hierarchic structure. The pre-layout simulation is successful but the post-layout simulaton is not as expected. I don't know how to find the problem, because all the signal names (except for the top-most port) in the post-layout simulation are generated...
Hi, vitalsys:
I went through a similar designe coping with A-B signals 10 years ago, not using VHDL then. I think I understand your application well. Here is my solution to your problem. I did the synthesis and post-layout simulation and proved it works. The design consists 5 entities, the...
Yoda:
Is your application related with position-encoder? I have a way to work it out. VHDLguy is right, use more than one edge in one process can be dangerous.
We can design 4 similar entities, each is a counter.
Counter 1 works only on A's rising edge, it increases or decreases according to...
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