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Hi a division 32 by 32 in 32 cycles scuse me for french inside.... best regards -- Division.vhd library IEEE; use IEEE.Std_Logic_1164.all; use IEEE.Std_Logic_arith.all; use IEEE.Std_Logic_unsigned.all; Entity Division Is port( Clock : in std_logic; Reset : in...

Hi All, I'm looking for a Vhdl for a Graphic LCD 4 Bits, whith CL1, CL2, FLM, M . in monochrome. (HITACHI SP10Q003-T) Have you some code. Best regards Christophe Darnet

Hi VHDLGuy, I know for one EVENT by process.. I have read some topic in this forum. now, in my source code I have 4 Procres.. But it's a same probleme.... A is a square ware (10khz) B is a square ware (A with 90°) _____ ______ A => ___| |______| |_____...

Hi All, I have 2 Signal INPUT_A and INPUT_B. And I want Inc/Dec a variable with this signals Process (INPUT_A,INPUT_B,Reset) Begin If Reset = '1' Then -- Async reset etc Else If Falling_Edge(INPUT_A) Then If INPUT_B='1' Then Variable <=...

Hi VHDLguy, no I want one shoot, my "if VarL>=X"3FC0" Then" is in a "case Status_r" when Attente3EME => if X >= X"3FC0" then --- Generate Interrupt Status_r :=Attente2EME; End If; If you have...

hi all, I like generate a Interrupt (output) in VDHL ------| |----- |_| an interrupt of 500ns to 1us (no problem) (I have a Clock in my design) I have in my design if VarL>=X"3FC0" Then -- Here I want generate a Interrupt -- may be by one another signal or other...