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Problem with simple(ish) counter
You are quite right to correct me, VHDLguy. The logic I meant to write was: clk_hold <= ((clk and not hold) or clk_hold) and clk; (I have deleted the last 'not') so clk_hold is set when the clock goes high but hold is low, and clears when clk falls. clk_hold is then the desired_output of... -
Problem with simple(ish) counter
Hmm... I know no VHDL. It seems that all you are asking for is an asynchronous S-R flip-flop on the clock to the counter. in abel: clk_hold = ( (clk & !hold) // set term # clk_hold ) // hold term & !clk; // over-ride reset // [& = and, # = or, ! =...
