Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

Register Log in
  • Congratulations SkipVought on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

Search results for query: *

  1. vitalsys

    multiple clocks

    I am trying to implement a counter that will inc. or dec. based on 2 clock sources. the following is the simplified code. CLK_A and CLK_B are 90 degrees out of phase. I am getting the error "Signal Q_IN cannot be synthesized, bad synchronous description". using xilinx webpack 6.1.03i. will...

Part and Inventory Search

Back
Top