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Unable to initialize RAM module
Thank you for your reply Senjed, I am currently away from my work station but was just wondering if you could expand on why one is unable to assign signal in two processes. I am a beginner to VHDL and do not own a book on the subject either so I am not familiar with some of the basic... -
Unable to initialize RAM module
Hi, I am using Xilinx's ISE Webpack software to make a FIR filter. I have already designed the memory control module and the ROM module to store my coefficients. I was able to initialise the ROM using a series of signal statements. However, my filter design uses a RAM to store the incoming...
