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Need help for Integer to std_logic_vector conversion.
Hi Berett, Thank you for your answer. Your solution works. I still don't understand why the CONV_STD_LOGIC_VECTOR function computes the two's complement only on 4 bits and not on 32 bits ( -7 -> x"00000009" ), but it doesn't really matter. The reason why I am using integers is that... -
Need help for Integer to std_logic_vector conversion.
Hello, I am having troubles with type conversions between integers and std_logic_vectors. I am using the following libraries : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; When I do : 1 - my_vect <= x"FFFFFFF9"; 2 - my_int... -
unable to generate a pulse on external pin event
Thanks for your answer. 1. fctrl_vld_l is NOT a periodic clock signal. It is an input pin of the FPGA that goes low only once. It does not necessary go low under a clock edge. (it is a pin used for host-fpga communications). 2. I have another periodic clock signal in my design. How can i... -
unable to generate a pulse on external pin event
Hello, I want to generate a pulse when the state of the pin FCTRL_VLD_L of my virtex xcv1000 FPGA changes from high to low. I tried: pulse : process begin wait until fctrl_vld_l'event and fctrl_vld_l='0'; pulsesignal <= '1', '0' after 100 ns; end process; This code synthetize, but when...
