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Adding and Subtracting Vectors
+ and - are arithmetic operators and can only be used with arithmetic types such as integer. When you declare a std_logic type. You must use logical operators such as OR, AND, NAND, etc.. Hope this helps M. -
Generic in VHDL , Help me please
I would like to design a component using generic. This component calls another component that is also using generic. example: U1: n_bit_adder generic map (width => 8) port map (a => word_A, b => word_b, c => carry_in, y => addition_result); In the previous example, the call for the component...
