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VHDL and Verilog using Sinplify
Hi everybody ! I've got a problem using Sinplify, and my instructor can't help me ! I try to synthetise a project with a top VHDL file which uses 2 components. The architecture of these components was synthetised in .vqm files (verilog quartus map) but when I synthetise the whole project... -
random number generator
Hi ! Just one suggestion : link your counter to a Look-Up-Table which contains a table of random number, and the value will be more unpredictable For example : Your counter counts 0-1-2-3-0-1-2-3.... Your table is 2-0-3-1 The output generated is 2-0-3-1-2-0-3-1.... So your counter... -
Compiling VHDL librairies
Hi ! I'm working on a huge VHDL project, and I want to use librairies to manage it simplier. I seen it's possible to group multiple VHDL files in one library. Is it possible to compile these VHDL files into a single library file ? And after use only this library file ? (I want to make...
