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  1. mavian

    Synthesizing VHDL function "*"

    When i try to synthesize this code using Synopsys I get a class violation saying that input pins are not connected. This is caused by the res_mant_add <= t_mant1 * t_mant2; in my code. And its the input to some adder. Does anyone know how to fix it? library IEEE; use IEEE.std_logic_1164.all...
    • mavian
    • Thread
    • Replies: 1
    • Forum: VHDL

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