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How fast is your clock? Even with three FF's you could be reacting to the input in a matter of nanoseconds. You can use a large counter to generate a clock-enable signal to sample the input at a much lower rate. The rate you need will depend upon your application. If you are physically...

You're links are dead so I can't check your code, but I'll take a stab at it anyway. Try mapping them to 'open' in the port map: port map ( unwanted_one => open, ut_fan => actual_signal, unwanted_two => open );

Have the master process control a mux for the output signal along with enabling the slave processes. entity_output <= process1_output when process1_enable = 1 else process2_output when process2_enable = 1 else process3_output when process3_enable = 1 else process4_output;

You need to define the array type in a package and then use the new type in your port. Here is a quick example I have compiled. This was done as a single file, but the package can be saves in a file by itself to be used in multiple places as a library. The result after compiling this example...

Since width appears to be a generic in your design, you should be able to use a GENERATE statement: assignment : if width <= 12 generate sigA((12-width) downto 0) <= sig_GND; end generate assignment;