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Type mismatch problem
Greetings! This is my first thread. I have a package that contains the following type: type t_rgb_64x48 is array(0 to 47) of std_logic_vector(63 downto 0); and is being used in my file.vhd file. ------------------------ file.vhd contains an entity that contains the type of the package...- thequickbrownfoxjump
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- Replies: 1
- Forum: VHDL
