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ghdl: no definition for "and" and "or" operator
Hi all, I'm using ghdl to compile some vhdl code and I can't get the "and" and "or" operators to work. Here's the file where I'm using it: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity question3 is Port (D :in std_logic_vector(3...
