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Problems with the Ands?
I am new in the programming in VHDL, and am doing a adder subtracter but me mistakes appear with the AND. 1 Library ieee; 2 Use ieee.std_logic_1164.all; 3 Entity Sumador_Restador is 4 port(A0,A1,A2,A3,B0,B1,B2,B3,E: In std_logic; 5 S0,S1,S2,S3,T0,T1,T2,T3,T4: Out std_logic); 6 End...- adytaKriss
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- Forum: VHDL
