Hi
I'm a newbie in VHDL. Like many people, i read the book: "VHDL: Learn by examples".
Then, i've been inspired to write for myself a kind FSM able to handle samples from an ADC in a RAM.
If you've got some spear time, i would be glad if you could have a look to the code i wrote (it is not...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.