library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_logic_signed.all;
entity ALU is
port(
A : in STD_LOGIC_VECTOR(7 downto 0);
B : in STD_LOGIC_VECTOR(7 downto 0);
funcSel : in STD_LOGIC_VECTOR(3 downto 0);
negative : out STD_LOGIC;
zero : out STD_LOGIC;
G : out...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity memory is
port (
rst : in std_logic; -- signal global
clock : in std_logic; -- signal global
read : in std_logic; -- Signal qui...
library IEEE;
use IEEE.std_logic_1164.all;
entity machine_top is
port(
clock : in STD_LOGIC;
rst : in STD_LOGIC;
IR : out STD_LOGIC_VECTOR(7 downto 0);
PC : out STD_LOGIC_VECTOR(7 downto 0);
RegA : out STD_LOGIC_VECTOR(7 downto 0);
RegB : out...
library IEEE;
use IEEE.std_logic_1164.all;
entity datapath is
port (
rst : in std_logic;
clock : in std_logic;
dataIn : in std_logic_vector(7 downto 0);
DA : in std_logic;
inputSelect : in std_logic;
load : in...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity controller is
port (
rst : in std_logic;
clock : in std_logic;
N : in std_logic;
Z : in std_logic;
memoryData...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.