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Some support for VHDL project
Hi, Many thanks for your support. Do you have idea how to implement automatic reset module. Some source code or advice will be appreciated. Kind regards, Boris- borissofia
- Post #4
- Forum: VHDL
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Some support for VHDL project
Hi Folks, I have to model following device ( http://alfist.hit.bg/task.jpg) via VHDL. First picture in attachment is taks seccond is my current result. CNT – 8 bit counter up form CLK fornt with asinchronus zero input. COMP – comparator for 2 8 bits digits. TRIG – D-trigger, synchronized...- borissofia
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- Replies: 3
- Forum: VHDL
