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execution speed
But since I choose to compile without optimization then all variables should go to memory. Thank you. -
execution speed
3- i and test are defined as 32 bit integer, so there will be no stretches over a word boundry, and those are the only variables i used in the for loop. 4- yes, its gcc. -
execution speed
1- I don't have some thing with 'char misalign', all what I have is i, test and they are unsigned integer 32 bit and PPC405 is a 32 bit device. 2- Compiler is set to no optimization. 3- Even if I have 'char misalign', why would it affect the timing of the for loop? the loop is independent from... -
execution speed
Could you explain more what do you mean? Can you give a sample code? Thanks. -
execution speed
Hello, I'm programming a PPC405 in c on a devolpment board, I didn't enable the cache and I set the compiler option to no optimization. I'm trying to measure the execution time for a simple for loop with a HW timer on an FPGA some thing like this: i, test is defined as unsigned integer 32 bit... -
cache disable for vertix II pro
Hello, I have a question regarding disabling the cache for the PPC405 in Vertix II Pro. When I start using the wizard to create a new project in XPS and during the process, there was an option to enable or disable the cache, but what if I would like to change that setting after finishing the... -
VHDL problem with variables
Hello, I've a problem when calling a procedure a passing variable to it, I tried my code in Quartus and compiled without errors but when I tried xilinx XPS which I have to use, I got the following error (undefined signal "aprio") The code is down, any help??? architecture rtl of mylogic is... -
For loop delay???
Hi all, If I assign a signal before a long for loop in a process, will that signal wait until the end of the process to take place? ie process (a) is variable cnt : std_logic_vector(0 to 15) :=X"0000"; begin active <= '1'; for i 0 to 1000 loop... -
signal assignment inside a for loop
Hello all, I'm new to VHDL and having a problem. I know that signal assignment does not take effect until the end of the process unlike the variable assignment. ie cnt <= cnt +1; out <= cnt; If cnt is a signal then out will have the value of cnt before adding 1. My...
