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  1. ditt0

    New to VHDL

    Hi all, I'm very new to VHDL n i need some help here. 1) the program sounds like this package abc is subtype counter_type is interger range 0 to ((2**13)-1); constant clock_cycle : counter_type :=8000; this first lines means my value will go from 0 to 8191, but why the second line...
    • ditt0
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    • Replies: 0
    • Forum: VHDL

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