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  1. dasjg

    Reply VHDL - FOR LOOP in VHDL testbench?

    I have the following VHDL testbench. How do i make a for loop that goes through :L_ADDRESS (4 down to 0)" I just want to be able to see L_ADDRESS change every 100ns in the wave viewer? --------------------------------------------------------------------- -- VHDL Test Bench Created from source...

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