Tek-Tips is the largest IT community on the Internet today!
Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!
-
Congratulations Mike Lewis on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!
-
Using float signal in VHDL
Jeandelfrigo, Thanks very much for your advice. Yes I need to get on a chip later so I have to write synthetisable code. Briefly, I have to carry software function in VHDL to gain speed. Part of this function are using mathematical stuff like trigonometric function, and other operations on... -
ERROR Definition
Hi Oppenheimer, I am sorry I dont have enought time to correct your code. I think you should start understanding what VHDL stands for. It is used to define an electronic circuit. So you need to have minimal basics in electronics. VHDL has nothing to do with any computing langage, the purpose is... -
ERROR Definition
Hi Oppenheimer, Happy it works!! I still do not understand why you put clk and rst on the same net. When using clocked process you usually have in the sensitivity list clock + reset. Reset is used to initialized signals, you can't use ':='operator to do that in real life (especially on entity... -
ERROR Definition
Hi Oppenheimer, I am not sure but I guess using 2 rising edge function in a single process to assign a unique signal bcd will not be liked by any synthetizer. Think about it you want to register a signal bcd and you want it to be registred with 2 different clocks I can't see how it can work. I... -
Using float signal in VHDL
Hi, I have to implement mathématical function in VHDL. That function was previously done in C and uses floating point as input and output. I wonder how to simply deal with floating point in VHDL. It does not seem to be a predefined type from VHDL packages and I see 2 ways of doing it: -...
