Hi all,
I've trying to simulate a simple state machine with VHDL code below:
library ieee;
use ieee.std_logic_1164.all;
entity p82 is
port(a, c, clk, rst: in std_logic;
x: out std_logic);
end p82;
architecture behavior of p82 is
type state is (stateA, stateB);
signal pr_state...
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