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Division in VHDL with std_logic_vector
This is the code i used: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity imp is Port ( in1 : in STD_LOGIC_VECTOR (7 downto 0); in2 : in STD_LOGIC_VECTOR (7 downto 0); ies : in STD_LOGIC_VECTOR (7... -
Division in VHDL with std_logic_vector
I need to implement a chaotic function in a design with VHDL. I use std_logic_vector signals and I need to implement 4 divisions. However, i recieve an error message saying: "Line 40. / can not have such operands in this context." I use: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use...
