Tek-Tips is the largest IT community on the Internet today!
Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!
-
Congratulations derfloh on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!
-
How do I design a race timer in VHDL ?
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity timer is port ( clk_in: in STD_LOGIC; reset: in STD_LOGIC; push_button: in STD_LOGIC; current_state: out STD_LOGIC_VECTOR (1 downto 0); digit0: out... -
How do I design a race timer in VHDL ?
The aim of this experiment is to design and construct a race timer, suitable for use in track events, where the times of place getters are displayed on seven segment LED displays. The circuit is to start counting on receipt of a pulse from a starting button, and to record the times of arrival of...
