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subtype(argument) is a type-conversion?
Hey. I have a book containing an example that goes: subtype dlx_address is unsigned(31 downto 0) PC:= dlx_address(signed(var1) + signed(var2)) My questions is, what does it do when you use the syntax: SUBTYPE(ARGUMENT). Is it just a type-conversion or what?- klauspetersen
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- Forum: VHDL
