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  1. Olivier2412

    Generate a 2 µs high level logic with a 10 MHz clock ?

    Hi ! I am using an ACTEL ProAsic Plus Starter Kit with an APA300 for the FPGA. I would like to optimize the VHDL and I am asking the following question : To command an ADC, I need to generate a SAMPLE signal (high logic during at least 2 µs) but my whole design runs at 10 MHz. To generate it...

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