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FIR filter error when Synthesized
Hi, I wrote a VHDL code for a 4 tap fir filter. I am not getting errors when I compile and simulate using altium designer. but when I put in Xilinx ISE 9.2i I'm getting an error saying " Line 34. Choices for an array aggregate (Attribute name) must be locally static unless there is only one... -
ROM addresses are read the other way around
I have a parallel to serial converter which connects to three series shift registers. this connects to a ROM. the ROM addresses are read by taking bits from the parallelto serial converter output,and from the outputs from each shift register. my problem is I am reading the addresses the other...
