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  • Users: borissofia
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  1. borissofia

    Some support for VHDL project

    Hi Folks, I have to model following device ( http://alfist.hit.bg/task.jpg) via VHDL. First picture in attachment is taks seccond is my current result. CNT – 8 bit counter up form CLK fornt with asinchronus zero input. COMP – comparator for 2 8 bits digits. TRIG – D-trigger, synchronized...

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