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  • Users: nyep
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  1. nyep

    VHDL While Loop Problem

    I am currently trying to compile and simulate a vhdl ROM file. I am having problem with the while loop, which is used to read the ROM. The following is the vhdl-code: entity mc8051_rom is generic (c_init_file : string := "mc8051_rom.dua"); port (clk : in std_logic; -- clock signal reset : in...
    • nyep
    • Thread
    • Replies: 3
    • Forum: VHDL
  2. nyep

    How to design a microcontroller using VHDL?

    hi, i just started my project, which is to design a microcontroller using VHDL. Can anyone tell me, what are basic steps to design a microcontroller? I only have basic knowlegde in Microcontroller. My Professor have also spoken about a microcontroller soft-core? Can anyone explain to me what...
    • nyep
    • Thread
    • Replies: 5
    • Forum: VHDL

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